DESIGN VERIFICATION ENGINEERS

Job Description of Design Verification:

1. Chip level verification, SV/UVM Methodology

2. Ethernet/ AXI/ PCIe protocols and Seeded

3. Exposure to any of these scripting language - perl/ bash-shell /python

4. Have lots of debugging skills to quickly scan and identify issues in system verilog/ verilog, C- code

5. Good in tool usage for simulation ( VCS), waveform debug ( Verdi)